Keynotes - Invited Talks

Wednesday, October 16, 2024, 8:10 - 8:40

Dr. Saifi Usmani, Merck  

Development and Implementation of a Data Ecosystem to enable End-to-End Advanced Predictive Manufacturing using AI

As the demand for electronic products increases, semiconductor manufacturers are integrating legacy and new materials into their manufacturing processes. However, the sheer volume of electronic components required to meet global demand has placed further emphasis on eliminating materials-related productivity and yield killers. Downstream materials suppliers are expected to provide increasingly sophisticated materials with predictive performance to customers at competitive pricing, creating a need for a data ecosystem that can support end-to-end advanced predictive manufacturing. 

To provide more predictive performance and eliminate the risk of quality disruptions, we have embarked on a full digitization and digitalization initiative to fully characterize our target processes and automate data capture. We have implemented technical approaches and production improvements to enhance our capabilities in this area. By extending an AI-driven quality approach to the broader supply chain and data ecosystem, we believe end-to-end advanced predictive manufacturing can be accelerated for the semiconductor industry. 

In this presentation, the Head of Merck Electronics’ Planarization Business, Saifi Usmani, will discuss the development and implementation of our data ecosystem, including the technical approaches and production improvements we have implemented.
We will also discuss the benefits of extending an AI-driven quality approach to the broader supply chain and data ecosystem, and how this can improve end-to-end advanced predictive manufacturing in the semiconductor industry.  

Thursday, October 17, 8:10 – 8:40

Alberto Pirati, ASML, The Netherlands

Lithography roadmaps

Secular trends like the widespread adoption of Artificial Intelligence, novel process integration technologies and governments drive towards increased technology sovereignty are redefining the markets for lithography equipment.

Lithography roadmaps are expanding in scope and complexity to deal with a growing range of requirements, driven by new technology challenges, and the need to supply different and expanding markets while extending the use and scope of the install base.

This paper presents an overview of the historical and future evolution of lithography roadmaps, and will zoom in the implications of novel process integration technologies like wafer to wafer bonding.

Friday, October 18, 8:00 – 8:30

Prof. Dr. rer. nat. Harald Kuhn, Fraunhofer Institute for Electronic Nano Systems ENAS, Chemnitz, Germany

Challenges for hetero integration process technology, test and reliability

The dynamic field of semiconductor technology necessitates innovative strategies to address the complexities of hetero-integration process technology, testing and reliability. This presentation examines key facets, with an emphasis on two pivotal areas for a variety of micro assembly applications:

A fundamental component in the development of heterogeneous integrated systems is the application of chemical mechanical planarization (CMP). This section explores the intricacies and advancements in CMP techniques, underscoring their essential role in achieving high precision and surface uniformity crucial for hetero-integration. It provides an in-depth look at the latest CMP technologies and their implications for semiconductor device performance.

Another critical area of focus is the integration of artificial intelligence (AI) and digital twins within CMP processes. This involves investigating how AI-driven digital twins can significantly enhance process control and optimization in semiconductor manufacturing. By utilizing predictive modeling and real time data analysis, these technologies enable more accurate control, reduce defects and increase efficiency in CMP operations.

Ensuring the quality and reliability of these complex heterogeneous integrated systems remains a top priority. This section addresses the distinct challenges and established methodologies for testing and ensuring the long-term reliability of advanced semiconductor devices. It discusses innovative approaches for verifying functionality and durability in these complex systems under various operating conditions.

Through the exploration of these key areas, this presentation provides valuable insights into the intricacies and solutions associated with hetero-integration, driving innovation, research and future advancements for use with the next generation semiconductor test applications. The increasing complexity of these systems requires new solutions for testing, such as design for test (DfT) and known good die (KGD) leading to more robust and reliable semiconductor applications.